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Modulated Reflectance Measurement of Reactive-Ion and Plasma Etch Damage in Silicon Wafers

机译:硅晶片中反应离子和等离子体蚀刻损伤的调制反射率测量

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摘要

Reactive ion etching (RIE) and plasma etching (PE) are vital processes for the attainment of densely-packed, micron-scaled structures for VLSI integrated circuits. However, it is widely recognized that undesirable modifications of semiconductor or insulator materials may accompany the use of these dry etch processes. For example, during the RIE process, samples are exposed to high energy ions, UV photons and x-rays, all of which can result in radiation damage [1] in the form of non-annealable structural defects in gate oxide or Si/Si02 interface regions, deep level traps or surface states. In terms of IC device performance, these effects cause transistor threshold voltage shifts, poor subthreshold performance, increased junction leakage or decreased capacitor charge retention time, degradation of minority carrier lifetime, barrier shifts in Schottky diodes and reduction of the integrity of trench isolation structures [2,3]. Contamination from sputtering of the chamber parts or of the oxide mask may add to these problems. In addition, polymer material that may be deposited from carbon-containing gases has been found to create oxygen-induced stacking faults [4]. All of the above can lead to significant yield reduction.
机译:反应性离子刻蚀(RIE)和等离子刻蚀(PE)是获得用于VLSI集成电路的致密堆积,微米级结构的重要过程。然而,众所周知,半导体或绝缘体材料的不希望的修改可能伴随着这些干法刻蚀工艺的使用。例如,在RIE过程中,样品暴露于高能离子,紫外线光子和X射线,所有这些都可能导致辐射损伤[1],形式为栅氧化物或Si / SiO2中不可退火的结构缺陷。界面区域,深能级陷阱或表面状态。就IC器件性能而言,这些影响会导致晶体管阈值电压漂移,不良的亚阈值性能,结漏电流增加或电容器电荷保持时间缩短,少数载流子寿命降低,肖特基二极管的势垒漂移以及沟槽隔离结构完整性的降低[ 2,3]。腔室部件或氧化物掩模的溅射污染可能会增加这些问题。另外,已经发现可能从含碳气体中沉积的聚合物材料会产生氧气引起的堆垛层错[4]。以上所有因素都会导致产量大幅下降。

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